1. Field of the Invention
The present invention relates to a semiconductor nonvolatile memory apparatus having a differential type cell in which data can be electrically written.
2. Description of the Related Art
A differential type cell for use in a nonvolatile semiconductor memory apparatus, may be formed a using two transistors/cell as illustrated in FIG. 1. In this example, the cell employs an N channel FAMOS (Floating gate Avalanche injection MOS) used in an ultraviolet erasable read only memory (EPROM).
In FIG. 1, reference numerals 11 and 12 designate transistors of N channel FAMOS configuration which constitute the two transistors of the differential memory cell. In the normal mode, one of the transistors 11 and 12 is in its ON state and the other is in its OFF state. Reference numerals 13 and 14 designates a pair of bit lines, 15 a word line and 16 and 17 column selecting transistors, respectively.
Further, in FIG. 1, reference numerals 18 and 19 designate dummy cells (placed in ON state constantly), 20 and 21 N channel transistors, 22 and 23 body cell selecting transistors, 24 and 25 dummy cell selecting transistors, 26 and 27 bias circuits for carrying out the level shift, 28 a differential amplifier type sense amplifier, 29 and 30 load transistors, 31 and 32 or 33 and 34 load adjusting transistors and 35 and 36 sense lines, respectively. A.sub.X2 is a gate input signal for switching dummy cell selecting transistor 24 and A.sub.X2 is a gate input signal for switching dummy cell selecting transistor 25. A.sub.X3 is a gate input signal for switching load adjusting transistor 31 and /A.sub.X3 is a gate input signal for switching load adjusting transistor 33. The output of a column decoder (not shown) is applied to the gates of column selecting transistors 16 and 17 for selecting bit lines 13 and 14. When the transistor 31 is turned ON in the test mode, the transistor 31 and the circuit of the transistor 32 become parallel to the transistor 29 to thereby increase the potential of the sense line. The transistors 30, 33 and 34 are placed in a similar relationship.
In the circuit of FIG. 1, the two transistors/cell of the transistors 11 and 12 are differentially operated such that one is operated as ON cell (non-programmed cell) and the other is operated as OFF cell (programmed cell) to supply the potential through the bit line and the bias circuit to the sense lines 35 and 36. Since the cells are operated differentially, the bit lines 13, 14 and the sense lines 35, 36 also are operated differentially, whereby the content of the cell can be propagated at high speed by the sense amplifier 28.
In the above-mentioned two transistors/cell system, the two transistors are operated differentially so that, if the threshold voltage is increased by a very small threshold voltage shift in the DC operation, then the sense amplifier 28 determines that the writing is finished. However, in the high speed access mode, that is, the AC operation mode, a constant amount of the threshold voltage shift is necessary, and in order to check the reliability, it is important to monitor the threshold voltage shift in the cell. In the die sort stage of the manufacturing process or in a commercially available programmer (writing device), the threshold voltage shift is generally checked in substantially the DC operation at low speed. In FIG. 1, in addition to the body cell, the dummy cells 18 and 19 are provided to check the above-mentioned threshold voltage shift. Logic levels of the signals relevant thereto at that time are represented in FIG. 2. If the logic levels are selected as shown in FIG. 2, then an intermediate level occurs in the level of the sense line (35 or 36) of the side which is not checked to thereby check the content of the cell.
In such conventional circuit, the switching transistors 22 and 23 whose gate inputs are A.sub.xl, A.sub.x1 must be provided between the bit line and the sense line. However, these switching transistors 22 and 23 operate as resistance elements to cause the speed of the bit line data to be decreased.
Accordingly, in order to omit the above-mentioned transistors 22 and 23, the column decoder may be divided into left and right column decoders to carry out the above-mentioned operation. In this case, however, the threshold voltage shift of the column decoder outputs is doubled (the wiring is generally made by a bilayer aluminum at a large pitch), which becomes disadvantageous from an integrated circuit area standpoint. Further, since the dummy cell and a peripheral transistor are manufactured by different manufacturing processes, the dummy cell and the peripheral circuit must be isolated by a constant distance, which unavoidably results in a large integrated circuit area.